1. Field of the Invention
The present invention relates to a data processing apparatus and, more particularly, to error correction of data.
2. Related Background Art
In a transmission system (including a recording and/or reproducing system) of digital data, transmission errors are detected and corrected by error detection/correction codes.
That is, an error detection/correction coding circuit to add an error detection/correction code is provided at the transmission side. A data reproduction processing circuit for detecting and correcting transmission errors by the error detection/correction code and for interpolating uncorrectable errors is provided at the reception side.
A construction of a conventional data processing apparatus for performing error detection and correction will now be described hereinbelow with reference to FIG. 1.
FIG. 1 is a block diagram showing a construction of the conventional data processing apparatus.
In FIG. 1, data (code train) which has been error detection/correction encoded and includes transmission errors at a predetermined probability by the transmitting system is supplied to an input terminal 10.
The above data (code train), for example, is provided from a reproduction head output of a digital video recorder, a reception signal from a digital communication line, or the like.
A data reproduction circuit 11 demodulates the data (code train) from the input terminal 10 and separates each sync block by a sync code of the sync block and recognizes an ID of the sync block.
The data (information data and a parity for error detection/correction) reproduced by the data reproducing circuit 11 is written into a data memory 12 in accordance with the recognized ID.
The reproduction data (code train) generated from the data reproduction circuit 11 is also supplied to a syndrome calculation circuit 13.
In accordance with a well-known method, the syndrome calculation circuit 13 calculates a syndrome for each of the error correction code which is constructed by a plurality of transmission codes and sequentially writes the syndromes of the error correction codes into a syndrome memory 14.
With reference to the memory contents in the syndrome memory 14, an error processing circuit 15 detects and corrects error data (codes) stored in the data memory 12.
In the case where the error data cannot be corrected, a concealment flag is written into the corresponding memory location in the data memory 12.
Practically speaking, first, the error data (codes) are detected with reference to the syndromes stored in the syndrome memory 14. In the case where the error data is correctable, the positions of error and the error pattern are calculated, data (codes) in the data memory 12 is corrected by using the result, and the corrected data is again written into the data memory 12.
In the case where the error data is uncorrectable, the error data in the data memory 12 is held without changing and a concealment flag is newly written into the data memory 12 for a code train including error codes. Specifically speaking, the error processing circuit 15 is constructed by a general digital arithmetic operating circuit in which microprograms and microcodes to execute the above error processes have been loaded and its function can be changed or modified by changing the microprogram.
After completion of the error process by the error processing circuit 15, the data and concealment flag stored in the data memory 12 are sequentially read out and are transmitted from an output terminal 16 to a circuit at the post stage (for example, an interpolation circuit to interpolate the uncorrectable error data).
Such a data processing apparatus is built in the reproducing system of a digital video tape recorder (hereinafter, also simply referred to a VTR).
The error detecting/correcting processes in the digital VTR are described below.
FIG. 2 shows a recording format of one line in the digital VTR. FIG. 3 shows a recording format of one track.
As shown in FIG. 2, one line is constructed by: sync data; an ID; information data of m symbols; and an error detection/correction code (inner code parity) of (n-m) symbols for the information data.
In one track, the code trains of FIG. 2 are comprised of a plurality of lines which are laterally arranged and outer codes are formed in the vertical direction.
A product code block of the error detection/correction is formed by an inner code and an outer code. The transmitting order of signals coincides with the direction of the inner code in FIG. 3.
The error detecting/correcting operation will now be described hereinbelow with reference to a flowchart of FIG. 4. The error correction code is a code which can correct two errors.
Syndromes of the inner code and outer code with respect to each reproduction code train are calculated and stored into the syndrome memory 14.
After the syndromes (q inner code syndromes and m outer code syndromes) of one track are written, the processing flow is started.
First, the error detecting/correcting processes of the inner code are executed.
That is, the syndrome of the first line is read out from the syndrome memory 14 (step S1) and the presence or absence of errors is discriminated (S2).
When one error exists, the one error is corrected (S3, S4). In case of two errors, the two errors are corrected (S5, S6). In case of three or more errors, since they are uncorrectable, a concealment flag is set (S7) and the processing routine advances to the process of the next line. When no error exists, the processing routine also advances to the process of the next line without executing a process. The above processes are executed with respect to P lines of the inner codes (S8, S9).
After completion of the error detecting/correcting processes by the inner code, the error detecting/correcting processes by the outer code is started.
The processes regarding the outer code are fundamentally the same as those for the inner code. With respect to each column, the syndrome of the outer code is read out from the syndrome memory 14 (S10) and the presence or absence of errors is discriminated (S11).
In case of one error, the one error is corrected (S12, S13). In case of two errors, they are corrected. In case of three or more errors, since they cannot be corrected, a concealment flag is set (S16). The processing routine advances to the processes of the next column. When there is no error, the processing routine also advances to the processes of the next column without performing a process.
The above processes are executed with respect to m columns of the outer code (S17, S18).
After completion of the processes of the outer code, a concealment flag as a result of the decoding of the inner code train and outer code train is written into the data memory 12 (S19).
The error detection/correction processing operation of data is executed as described above.
The data whose errors cannot be corrected by the above error detecting/correcting circuit in the data supplied from the output terminal 16 can be error corrected by interpolation.
In an electromagnetic converting system such as a VTR, however, there is a case where a burst error occurs due to a choking of a head or a scratch on a magnetic tape and an error ratio rapidly deteriorates.
For instance, it is now assumed that errors as shown in FIG. 6 occurred in a recording and/or reproducing apparatus for recording and/or reproducing image data (information data) onto/from a magnetic tape by a recording format as shown in FIG. 5.
In FIG. 6, it is assumed that burst errors occurred at all of the positions shown by two lateral lines (a and b) and two vertical lines (c and d) each of which is formed by connecting two marks "x".
In such a case, to perform the error detection and correction by the inner code, it is necessary to execute two-correcting processes of 94 code trains excluding the lateral lines a and b and an uncorrectable error process of two code trains of the lines a and b.
The 2-correcting process of 94 code trains is needed for the error detection/correction by outer codes.
FIG. 7 shows the number of steps (numerical value on the right side in each block) in an error detecting/correcting step corresponding to the flowchart of FIG. 4.
It is now assumed that the number of steps of the time which can be divided in one track for the error detecting/correcting processes of the inner code and outer code is set to 20,000 steps. The number of steps to detect/correct errors in the case where error data as shown in FIG. 6 occurred. For the two-correcting process of the inner code, 11,280 steps are needed, and for the uncorrectable error process, 40 steps are needed. For the two-correcting process of the outer code, 11,040 steps are needed, and for the writing process of the concealment flag, 960 steps are needed.
That is, the time of 23,320 steps are necessary per track and such a time duration exceeds the time which can be allocated per track, so that an adequate time to write the concealment flag into the data memory is lacking.
According to the conventional apparatus as mentioned above, in the case where a number of errors occurred, the concealment flag cannot also be written, so that there occurs a problem such that in the case where the error uncorrectable code is image data, even if the operator tries to interpolate such uncorrectable image data by the post stage, there is no surplus time to execute the interpolation.